Switching regulators are used to regulate DC voltages and to convert one DC voltage to another, by stepping the voltage either up or down, or with the ability to step the voltage up or down depending on changing conditions. The quality of a DC/DC switching converter and regulator is measured by its ability to regulate over a range of input voltages, output voltages, load currents and temperatures. It should react sufficiently fast to guarantee good regulation during voltage and current transients as well as during steady state operation. In some applications it should also provide electrical isolation to prevent high input voltages from coupling to the output terminal, eliminating the risk of electrical shock and fire.
Most switching regulators utilize an inductor or coil as an energy storage device, since an inductor easily generates a range of output voltages different from the input voltage that drives, i.e. magnetizes, the inductor. Along with diode rectifiers, one or more power switches, typically power MOSFETs, whose switching and conduction are controlled by a pulse-width modulation (PWM) controller, are used to control the current in the inductor and, by using negative feedback, the output voltage of the regulator. Some examples of well-known prior-art DC/DC converting regulators are illustrated in FIGS. 1A-1F.
Common DC/DC Converter Topologies: In FIG. 1A, a Buck converter 1 provides step-down voltage regulation whereby, through pulse-width modulation, a high-side power MOSFET 2 controls the current in an inductor 4 in response to a PWM controller 7. A capacitor 5 filters the voltage ripple on the output terminal of converter 1. When high-side MOSFET 2 is off, the current in inductor 4 is maintained because the voltage Vx drops below ground, forward biasing rectifier 3 and allowing the inductor current to recirculate until MOSFET 2 is turned on again. A diode 6 remains reverse-biased under normal operation. As shown, MOSFET 2 is a P-channel device, but a high-side N-channel MOSFET may be substituted for the P-channel device with appropriate changes in the gate drive circuitry.
FIG. 1B illustrates a synchronous Buck converter 10 with a PWM controller 17, a high-side P-channel MOSFET 11 with an intrinsic P-N diode 15, an inductor 13, and a capacitor 14. The synchronous rectifier comprises an N-channel MOSFET 12 with an intrinsic P-N diode 16. A break-before-make (BBM) circuit 18 is included to prevent simultaneous conduction in both high-side P-channel MOSFET 11 and low-side N-channel synchronous rectifier MOSFET 12. Operation of synchronous Buck converter 10 employs the same control and feedback techniques as described for non-synchronous Buck converter 1 except that MOSFET 12 conducts during a portion of the time diode 16 is conducting, i.e. when MOSFET 11 is off.
While synchronous Buck converter 10 employs a complementary half-bridge, with MOSFET 11 a P-channel and MOSFET 12 an N-channel, asynchronous Buck converter 20 of FIG. 1C utilizes an N-channel totem-pole arrangement comprising an N-channel high-side MOSFET 21 and an N-channel low-side synchronous rectifier MOSFET 22.
Boost converter 30, shown in FIG. 1D, comprises a MOSFET 31 and a PWM controller 36, controlling the current in an inductor 32 through pulse width modulation or by controlling the on-time of MOSFET 31 in variable-frequency operation. Whenever MOSFET 31 is off and inductor 32 is not being magnetized, the voltage Vx flies up, forward-biasing a rectifier diode 33 and supplying current to a filter capacitor 34 and the output terminal. Feedback of the output voltage Vout via a feedback voltage VFB is used to control the on-time of MOSFET 31, the current in inductor 33, and Vout. A synchronous boost regulator, a modification of boost converter 30, includes an N-channel or P-channel synchronous rectifier MOSFET placed in parallel with diode 33 to shunt current from diode 33 during some portion of the time when diode 33 is forward-biased, i.e. when low-side MOSFET 31 is off.
Typical for switching regulators employing a single inductor rather than a transformer or coupled inductor, the Buck and synchronous Buck converters shown in FIGS. 1A-1C can be used only for step-down voltage conversion, i.e. reducing an input voltage to a lower and well-regulated output voltage. The converse of the Buck converter, the boost converter shown in FIG. 1D and a corresponding synchronous boost converter can be used only for step-up voltage conversion, i.e. increasing an input voltage to a higher and well-regulated output voltage.
To obtain a single regulator with the ability to step an input voltage either up or down requires a more complex solution, using either double the number of power MOSFETs to combine a Buck and boost converter into a single circuit, or by employing multi-winding inductors and transformers. For example, in the converter 40 shown FIG. 1E, a high-side MOSFET 41 drives a coupled inductor 42 with a turns-ratio of “n”, the secondary side of which is rectified by one, two, or four rectifier diodes or synchronous rectifier MOSFETs to output a voltage across a capacitor 44. To regulate the output voltage, the output voltage Vout must be fed back to a PWM controller 47 via a feedback voltage VFB across an isolation barrier 46 which may comprise a transformer or an opto-coupler.
While converter 40 utilizes a P-channel power MOSFET connected to positive input voltage Vcc, converter 50 shown in FIG. 1F uses a grounded N-channel MOSFET 51 to control the current in a coupled inductor 52, whose secondary winding is rectified by a diode or MOSFET rectifier circuit 53 and filtered by a capacitor 54. The output voltage across capacitor 54 is fed back to the primary side PWM controller 57 through an isolation transformer or opto-coupler 56. Converter 50 may operate as a forward converter or as a flyback converter, depending on whether energy is transferred to the load in phase, when MOSFET 51 is conducting, or out of phase, when MOSFET is turned off.
In all of the regulators shown in FIGS. 1A-1F, power MOSFETs and rectifier diodes are used to control the energy flow in the converter and regulating circuit. In synchronously rectified converters, even the diodes are shunted by conducting MOSFETs to reduce conduction losses.
But switching a power MOSFET at frequencies over one megahertz involves switching and gate drive power losses, not just power lost due to conduction.
Conduction and Switching Losses in Power MOSFETs: Even though power MOSFETs offer superior electrical performance to other semiconductor devices, especially for operation below 100 volts, they are not ideal power switches—they do in fact dissipate power and reduce the efficiency of the circuit in which they are employed. In a conducting or on-state, the power dissipated is determined by the voltage across the drain-to-source terminals times the current, or P=ID·VDS. Since the device is not conducting all of the time, the average power is determined by the percentage of the clock period T that the device is on and conducting, i.e. ton/T.
In the main switch of as DC/DC switching regulator this fraction is also referred to as the duty factor D of the converter. It is well known to those skilled in the art that if the circuit is not operating at a fixed frequency f≡1/T, then its cycle-by-cycle average power changes, and a more careful time-integration must be performed to calculate the device's average power dissipation over longer durations, e.g. during the discharge of a LiIon battery.
The power dissipation in a conducting, “on” state power MOSFET depends on its terminal voltages. The terms “on” and “switch” should not be construed to mean or imply exclusively digital operation. Power MOSFETs may operate as either a programmable current source or as a variable resistance. The term “switch,” as used herein, follows the IEEE and Webster dictionary definition as referring to a device that completes or interrupts an electrical circuit, i.e. allowing or preventing current flow, without regard to the magnitude of that current.
In its saturation region of operation, an “on” power MOSFET behaves like a constant current source Isat, depending on the gate voltage and relatively independent of the value of its drain voltage VDS. The average power dissipation is then given by
      P          cond      ⁡              (        sat        )              =            I      sat        ·          V      DS        ·                  t                  on          ⁡                      (            sat            )                              T      
Operating as a controlled current source, the magnitude of a power MOSFET's current must be held to a low value, or the device will overheat. Care must be taken in circuit design to minimize input voltage variations from affecting the device's gate bias. With gate control, the power MOSFET may be operated as a switched current source, alternating between a fixed drain current and an off condition where no current except for device leakage flows.
When a power MOSFET is used as low-resistance switch, the device operates in its “linear” region, which is characterized by a linear relationship between its drain voltage and its drain current, the slope of which defines a variable resistance RDS(on) whose magnitude varies with the MOSFET's gate bias. Since from Ohm's law V=I·R, the power dissipation in a MOSFET in its linear region follows the relationship
      P          cond      ⁡              (        lin        )              =                    I                  D          ⁡                      (            lin            )                              ·              V                  DS          ⁡                      (            lin            )                              ·                        t                      on            ⁡                          (              lin              )                                      T              =                            (                      I            D                    )                2            ·              R                  DS          ⁡                      (            on            )                              ·                        t                      on            ⁡                          (              lin              )                                      T            
The term RDS(on) assumes that the device is operating in its linear region, acting as a variable resistance depending on the gate voltage.
Power is also lost switching the power MOSFET on and off at high frequencies. FIGS. 2A-2D illustrate the power loss in a MOSFET that results from its gate capacitance. As shown in FIG. 2A, a transient gate current Ig(t) required to charge and discharge the capacitive gate of a MOSFET 61 is supplied by and lost in a gate buffer 63, first by charging the MOSFET's gate to turn it on, then subsequently to dump the charge stored on the MOSFET's gate to ground. The equivalent power loss from driving a capacitor is given by the well-known formula P=Ceq·V2. The term Ceq is used because the MOSFET exhibits multiple voltage variable capacitances intrinsic to its structure, making a simple power calculation using capacitance problematic at best. FIG. 2B illustrates a network of capacitance for a MOSFET 66 including a gate-to-source capacitance 70 (CGS), a gate-to-drain capacitance 69 (CDG), and a drain-to-source capacitance 72 (CDS) associated with P-N junction diode 71.
In addition to being voltage-variable, gate-to-drain capacitance 69 forms a feedback path from the MOSFET's drain “output” to its gate input. Any time the circuit shows voltage gain, this capacitance is also amplified, loading the input terminal with a capacitance many times larger than the magnitude of small-signal capacitance CDG. This phenomenon, known as the Miller effect, greatly complicates calculating power loss with capacitance since during a switching transient, MOSFET 66 passes from cutoff, into saturation, and into its linear region, with the voltage gain and capacitance all varying in tandem.
FIG. 2C illustrates one such switching transient overlaid atop a power MOSFET's ID−VDS family-of-curves. Specifically the “load” represents a switching regulator such as the Buck converter 1 of FIG. 1A driving both rectifier diode 3 and inductor 4 during diode recovery, i.e. when the diode ceases conduction and the MOSFET starts.
Starting with an “off” device having no current at point 78, the switching transient shown traverses path 71 at a relatively constant drain voltage. The drain-to-source voltage cannot change instantly because diode 3 must be depleted of any stored charge before the drain voltage can rise. With a large VDS drain voltage, VDS>VGS and the MOSFET is operating in its saturation region. The current in a saturated MOSFET ramps as controlled by the gate voltage 74 in proportion to the VGS value. In such a condition and circuit, the saturated MOSFET exhibits voltage gain, amplifying the gate-to-drain feedback capacitance by constantly changing and increasing amounts, making it increasingly harder for a gate buffer to smoothly drive the MOSFET's gate during the transition.
At a gate bias VGS5, the device enters operating condition 72 where both current and drain voltage are changing rapidly. Point 75 corresponds to a bias condition in the transition region between linear and saturation, sometimes called edge-of-saturation or quasi-saturation. Instantaneous power losses in the device have peaked and begin to decline as VDS drops. From gate bias VGS6 and higher, the MOSFET is operating in its linear region 76.
Further increases in gate voltage 73 lower the MOSFET's resistance RDS further to point 79 but with diminishing improvements in conduction loss. In the example shown, the current becomes semi-constant during this short interval because the load is inductive and will not allow current to charge instantly. Since ID, VDS and VGS vary simultaneously, it is difficult to account for all the intra-device currents.
While in an actual application, the gate buffer used to drive a MOSFET's gate behaves like a fixed voltage source, greater clarity in device operation can be gained with current-source gate drive. As shown in FIG. 2D, a current-source supplying a constant current IG to the gate of a MOSFET driving a load, produces a VDS switching transient that with time declines in voltage from Vcc at cutoff 83, through saturation 87, and into its linear region 88. During the same time, starting at zero volts at point 90, the VGS gate voltage increases linearly 81 during cutoff, reaches a plateau 82 in saturation when the drain voltage 87 is slewing, and increases again 83 as the device enters its linear operating region. At time ton, the transient is over, the MOSFET is fully conducting and the drain voltage is now ID·RDS. Since the gate current was constant during the entire transition and since Q=IG·ton then the x-axis may be re-plotted as gate charge QG.
Since charge is always conserved, the amount of charge needed to reach point 84 is independent of the gate drive circuit. In other words, the gate charge QG needed to reach a given gate and drain bias condition is path-independent and does change with drive circuitry. The graph of QG and VGS can be re-plotted with VGS on the x-axis as shown in graph 100 of FIG. 3A, having cutoff, saturation, and linear regions 104, 105 and 106 respectively. Plotted on the same axis the drain voltage is expressed as a resistance, declining rapidly 101 at the edge of saturation into linear region 102, and finally stabilizing at point 108 at a minimum value RDS.
The power loss to reach gate charge 107 and drain voltage 108 can then be expressedPdrive=QG·VGS·f 
This equation takes into account the Miller effect and all voltage dependent capacitances but varies with the drain bias VDS, with gate drive VGS, and with technology. The total loss of a power MOSFET used in a switching regulator can then be calculated by the equationPloss=Pcond(lin)+Pcond(sat)+Pdrive+Pother 
In conventional switching regulators, the MOSFET is never intentionally operated in saturation but only experiences saturation during the switching transients and diode recovery. In such cases, provided that the converter's frequency is not too high, Pcond(sat) can be neglected and only conduction losses in the linear region Pcond(lin) need be considered. At low voltages, miscellaneous losses Pother can be neglected and the power loss equation simplifies to
  P  =                              (                      I            D                    )                2            ·              R                  DS          ⁡                      (            on            )                              ·                        t                      on            ⁡                          (              lin              )                                      T              +                  Q        G            ·              V        GS            ·      f      Given the QG and RDS curves in graph 100, the overall power loss calculated using the above equation is shown in graph 120 of FIG. 3B for operation at a fixed ton/T ratio. As shown, curves 121, 122, and 123 illustrate that the power loss increases in proportion to the frequencies f1, f2, and f3, which may be, for example, 300 kHz, 1 MHz, and 2 MHz.
The power loss curve has a U-shape with a minimum value at some specific gate voltage and increases losses for any gate drive above or below that value. The gradual increase in Ploss at higher gate drive voltages is due to increased gate drive losses Pdrive consistent with curve 106 in graph 100. For low gate voltages, the steep dependence of Ploss with gate voltage is a consequence of MOSFET operation at the edge of saturation corresponding to curve 101 in graph 100. As frequency increases from curve 121 to 123, the minimum power loss increases, i.e. the converter exhibits decreased efficiency, and exhibits a greater concavity, i.e. its minimum occurs over a narrower range of gate voltage. In other words gate drive losses become increasingly critical at higher frequency operation.
In normal applications, where a constant voltage rather than a constant current drive is employed, the gate drive losses are not evident from inspection of the VGS switching waveforms because they occur too quickly to be visible. For example, in FIG. 4A, a gate buffer 141, comprising a P-channel MOSFET 142 and an N-channel MOSFET 143 and powered by a voltage source 146 providing a voltage Vcc, rapidly drives the gate of a power MOSFET 144 between Vcc and ground. During turn on, the VGS switching waveform 150 shown in FIG. 4B shows some slight slope change 153 in its otherwise smooth upward progression 151 and 154 and again during turn off reveals a slope change 157 in its smooth decay 156 and 158 to a final gate voltage 159 of zero volts.
A clearer mechanistic picture of the actual drive loss is shown in graph 170, also in FIG. 4B, where the gate charge increases linearly from a start value 171 of zero coulombs, rises with a slope 172, reaches a final value 173 and at time t3 decays 174 to a final value 175 of zero coulombs at the end of the switching transient. So even though the gate drive uses a constant voltage drive, the power loss is the same as shown using with a current source drive condition. The total charge stored on the gate during charging is all lost to ground during turn off.
Such rail-to-rail drive is lossy because it doesn't recycle or preserve any gate charge from cycle-to-cycle and because it drives the gate to a voltage Vcc which may not correspond to the minimum power loss condition shown in FIG. 3B. As a result, power is wasted by throwing charge away and by overdriving a MOSFETs gate, both factors lowering the efficiency of a converter.
What is needed in any MOSFET switched at frequencies, and especially in DC/DC switching regulators, is a means to charge and discharge the power MOSFET's gate so that some portion of the gate charge is preserved and reused on a cycle-by-cycle basis in order to improve the overall efficiency of the converter or other circuit.